1. Technical Field of the Invention
This invention relates generally to integrated circuits and more particularly to crystal oscillation circuits used therein.
2. Description of Related Art
As is known, all integrated circuits that include a processor component (e.g., a processor, a digital signal processor, a state machine, et cetera) require at least one clock signal. For high-tech integrated circuits, such as those used in wireless communication devices, the clock signal may have a rate in the hundreds of megahertz to tens of gigahertz. To produce such a high frequency clock signal, most processor based integrated circuits include a phase locked loop and/or a variation thereof (e.g., a fractional-N synthesizer).
As is also known, a phase locked loop includes a phase and frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a feedback divider. In operation, the phase and frequency detector compares the phase and/or frequency of a reference clock signal with the phase and/or frequency of the feedback clock signal (i.e., the desired high frequency clock signal divided by the feedback divider). If a phase and/or frequency difference exists, the phase and frequency detector generates an up signal or a down signal. The phase and frequency detector generates the up signal when the phase and/or frequency leads the phase and/or frequency of the feedback clock signal, which indicates that the rate of the desired high frequency clock is too slow. Conversely, the phase and frequency detector generates the down signal when the rate of the desired high frequency clock signal is too fast.
The charge pump converts the up or down signal into a current signal. The loop filter converts the current signal into a control voltage. The voltage control oscillator produces the desired high frequency clock signal based on the control voltage.
As is generally understood in the art, the reference clock signal needs to be stable for the phase locked loop to function properly. Typically, the reference clock signal is produced by a crystal oscillation circuit that includes a crystal oscillator, an inverter coupled in parallel with the crystal oscillator, and capacitors coupled to the input and output of the inverter and to ground. To conserve power, the crystal oscillation circuit includes an enable/disable mechanism. For example, the positive supply voltage connection of the inverter may be coupled to a power enable transistor that, when enabled, couples the positive supply voltage connection of the inverter to the power supply of the integrated circuit. Once enabled, thermal noise activates the oscillation of the crystal oscillation circuit.
To speed up the activation of the crystal oscillation circuit, the circuit may include an activation circuit that places the input and output of the inverter in known states at the activation of the crystal oscillation circuit. While such activation circuits work well, they consume integrated circuit die area, which, for the never ending quest for smaller die areas, is counter productive.
Therefore, a need exists for a crystal oscillation circuit with active start-up that requires minimal additional circuitry.